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MC33171, MC33172, MC33174, NCV33172 Single Supply 3.0 V to 44 V, Low Power Operational Amplifiers
Quality bipolar fabrication with innovative design concepts are employed for the MC33171/72/74 series of monolithic operational amplifiers. These devices operate at 180 mA per amplifier and offer 1.8 MHz of gain bandwidth product and 2.1 V/ms slew rate without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage includes ground potential (VEE). With a Darlington input stage, these devices exhibit high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC33171/72/74 are specified over the industrial/automotive temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic as well as the surface mount packages.
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PDIP-8 P SUFFIX CASE 626 1 SO-8 D, VD SUFFIX CASE 751
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14 1
PDIP-14 P, VP SUFFIX CASE 646
Features
* * * * * * * * * * * * * * *
Low Supply Current: 180 mA (Per Amplifier) Wide Supply Operating Range: 3.0 V to 44 V or 1.5 V to 22 V Wide Input Common Mode Range, Including Ground (VEE) Wide Bandwidth: 1.8 MHz High Slew Rate: 2.1 V/ms Low Input Offset Voltage: 2.0 mV Large Output Voltage Swing: -14.2 V to +14.2 V (with 15 V Supplies) Large Capacitance Drive Capability: 0 pF to 500 pF Low Total Harmonic Distortion: 0.03% Excellent Phase Margin: 60 Excellent Gain Margin: 15 dB Output Short Circuit Protection ESD Diodes Provide Input Protection for Dual and Quad Pb-Free Packages are Available NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes
14 1
SO-14 D, VD SUFFIX CASE 751A
14 1
TSSOP-14 DTB SUFFIX CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 10 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 9
1
Publication Order Number: MC33171/D
MC33171, MC33172, MC33174, NCV33172
PIN CONNECTIONS
SINGLE Offset Null Inv. Input Noninv. Input VEE
1 2 3 4 8
QUAD NC VCC Output Offset Null Output 1 Inputs 1 VCC Inputs 2 Output 2
1 2 3 4 5 6 7 14
Output 4 Inputs 4 VEE Inputs 3 Output 3
- +
7 6 5
- +
1
4
- +
13 12 11
(Single, Top View)
+ 2 -
3
+ -
10 9 8
DUAL Output 1 Inputs 1 VEE
1 2 3 4 8
(Top View) VCC Output 2 Inputs 2
5
- +
1 2- +
7 6
(Top View)
VCC Q3 Q1 Q2 R1 Bias - Inputs + C2 Q15 D3 Q19 Q13 Q12 D1 R5 R3 R4 Q14 Q16 Q8 Q9 Q10 Q11 C1 R2 D2 R6 R7 R8 Q17 Q18 Output Q4 Q5 Q6 Q7
Current Limit
VEE/GND Offset Null (MC33171)
Figure 1. Representative Schematic Diagram (Each Amplifier)
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MC33171, MC33172, MC33174, NCV33172
MAXIMUM RATINGS
Rating Supply Voltage Input Differential Voltage Range Input Voltage Range Output Short Circuit Duration (Note 2) Operating Ambient Temperature Range Operating Junction Temperature Storage Temperature Range Symbol VCC/VEE VIDR VIR tSC TA TJ Tstg Value 22 (Note 1) (Note 1) Indefinite (Note 3) +150 -65 to +150 Unit V V V sec C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL connected to ground, TA = +25C, unless otherwise noted.)
Characteristics Input Offset Voltage (VCM = 0 V) VCC = +15 V, VEE = -15 V, TA = +25C VCC = +5.0 V, VEE = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh (Note 3) Average Temperature Coefficient of Offset Voltage Input Bias Current (VCM = 0 V) TA = +25C TA = Tlow to Thigh (Note 3) Input Offset Current (VCM = 0 V) TA = +25C TA = Tlow to Thigh (Note 3) Large Signal Voltage Gain (VO = 10 V, RL = 10 k) TA = +25C TA = Tlow to Thigh (Note 3) Output Voltage Swing VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = Tlow to Thigh (Note 3) VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = Tlow to Thigh (Note 3) Output Short Circuit (TA = +25C) Input Overdrive = 1.0 V, Output to Ground Source Sink Input Common Mode Voltage Range TA = +25C TA = Tlow to Thigh (Note 3) Common Mode Rejection Ratio (RS 10 k), TA = +25C Power Supply Rejection Ratio (RS = 100 W), TA = +25C Power Supply Current (Per Amplifier) VCC = +5.0 V, VEE = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, TA = +25C VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh (Note 3) Symbol VIO Min - - - - - - - - 50 25 3.5 13.6 13.3 - - - Typ 2.0 2.5 - 10 20 - 5.0 - 500 - 4.3 14.2 - 0.05 -14.2 - Max 4.5 5.0 6.5 - 100 200 nA 20 40 V/mV - - V - - - 0.15 -13.6 -13.3 mA 3.0 15 VICR 5.0 27 - - V VEE to (VCC -1.8) VEE to (VCC -2.2) 80 80 - - - 90 100 180 220 - - - 250 250 300 dB dB mA mV/C nA Unit mV
DVIO/DT IIB
IIO
AVOL
VOH
VOL
ISC
CMRR PSRR ID
1. Either or both input voltages must not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. 3. MC3317x Tlow = -40C Thigh = +85C MC3317xV, NCV33172 Tlow = -40C Thigh = +125C
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MC33171, MC33172, MC33174, NCV33172
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL connected to ground, TA = +25C, unless otherwise noted.)
Characteristics Slew Rate (Vin = -10 V to +10 V, RL = 10 k, CL = 100 pF) AV +1 AV -1 Gain Bandwidth Product (f = 100 kHz) Power Bandwidth AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5% Phase Margin RL = 10 k RL = 10 k, CL = 100 pF Gain Margin RL = 10 k RL = 10 k, CL = 100 pF Equivalent Input Noise Voltage RS = 100 W, f = 1.0 kHz Equivalent Input Noise Current (f = 1.0 kHz) Differential Input Resistance Vcm = 0 V Input Capacitance Total Harmonic Distortion AV = +10, RL = 10 k, 2.0 Vpp VO 20 Vpp, f = 10 kHz Channel Separation (f = 10 kHz) Open Loop Output Impedance (f = 1.0 MHz) Symbol SR 1.6 - GBW BWp - fm - - - - - - - - - CS zo - - 35 60 45 15 5.0 32 0.2 300 0.8 0.03 120 100 - Deg - - dB - - - - - - - - - dB W pF % nV/ Hz pA/Hz MW 1.4 2.1 2.1 1.8 - - - MHz kHz Min Typ Max Unit V/ms
Am
en In Rin Cin THD
V ICR , INPUT COMMON MODE VOLTAGE RANGE (V)
VCC -0.8 -1.6 -2.4 0.1 VEE 0 -55 -25
VCC/VEE = 1.5 V to 22 V DVIO = 5.0 mV
Vsat , OUTPUT SATURATION VOLTAGE (V)
0
0 VCC -1.0 Source VCC/VEE = 5.0 V to 22 V TA = 25C
1.0 Sink 0 VEE 0 1.0 2.0 3.0 IL, LOAD CURRENT (mA) 4.0
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 2. Input Common Mode Voltage Range versus Temperature
Figure 3. Split Supply Output Saturation versus Load Current
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MC33171, MC33172, MC33174, NCV33172
A VOL , OPEN LOOP VOLTAGE GAIN (dB) 3 0 20 10 0 -10 -20 VCC/VEE = 15 V RL = 10 k Vout = 0 V TA = 25C 1 - Phase 2 - Phase, CL = 100 pF 3 - Gain 4 - Gain, CL = 100 pF 1.0 M f, FREQUENCY (Hz) Phase Margin = 58 2 4 3 200 220 10 M 0 10 20 50 100 200 CL, LOAD CAPACITANCE (pF) 500 0 1.0 k Gain 1 Margin = 15 dB 140 160 180 70 m, PHASE MARGIN (DEGREES) 120 , EXCESS PAHSE (DEGREES) 60 50 40 30 20 10 % fm VCC/VEE = 15 V AVOL = +1.0 RL = 10 k DVO = 20 mVpp TA = 25C 70 %, PERCENT OVERSHOOT 25 60 50 40 30 20 10
-30 100 k
Figure 4. Open Loop Voltage Gain and Phase versus Frequency
Figure 5. Phase Margin and Percent Overshoot versus Load Capacitance
1.3 GBW AND SR (NORMALIZED) 1.2 GBW 1.1 1.0 SR 0.9 0.8 0.7 -55 10 V/DIV 0 VCC/VEE = 15 V RL = 10 k
5.0 ms/DIV
50 mV/DIV
0
VCC/VEE = 15 V VCM = 0 V VO = 0 V DIO = 0.5 mA TA = 25C
-25
0
25
50
75
100
125 5.0 ms/DIV
TA, AMBIENT TEMPERATURE (C)
Figure 6. Normalized Gain Bandwidth Product and Slew Rate versus Temperature
Figure 7. Small and Large Signal Transient Response
z o , OUTPUT IMPEDANCE ( )
120 100 80 60 40 20
VCC/VEE = 15 V AV = +1.0 RL = 10 k CL = 100 pF TA = 25C
I D , I CC , POWER SUPPLY CURRENT (mA)
140 AV = 1000 AV = 100
1.1 1. TA = -55C 2. TA = 25C 0.9 3. TA = 125C 0.7 Dual 0.5 0.3 0.1 0 5.0 10 15 VCC/VEE, SUPPLY VOLTAGE (V) 20 Single 1 2 3 1 2 3 Quad 1 2 3
AV = 10
AV = 1.0
0 200
2.0 k
20 k f, FREQUENCY (Hz)
200 k
2.0 M
Figure 8. Output Impedance and Frequency
Figure 9. Supply Current versus Supply Voltage
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MC33171, MC33172, MC33174, NCV33172
APPLICATIONS INFORMATION - CIRCUIT DESCRIPTION/PERFORMANCE FEATURES Although the bandwidth, slew rate, and settling time of the MC33171/72/74 amplifier family is similar to low power op amp products utilizing JFET input devices, these amplifiers offer additional advantages as a result of the PNP transistor differential inputs and an all NPN transistor output stage. Because the input common mode voltage range of this input stage includes the VEE potential, single supply operation is feasible to as low as 3.0 V with the common mode input voltage at ground potential. The input stage also allows differential input voltages up to 44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between VCC and VEE supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the VCC voltage by approximately 3.0 V and decrease below the VEE voltage by 0.3 V without causing product damage, although output phase reversal may occur. It is also possible to source up to 5.0 mA of current from VEE through either inputs' clamping diode without damage or latching, but phase reversal may again occur. If at least one input is within the common mode input voltage range and the other input is within the maximum input voltage range, no phase reversal will occur. If both inputs exceed the upper common mode input voltage limit, the output will be forced to its lowest voltage state. Since the input capacitance associated with the small geometry input device is substantially lower (0.8 pF) than that of a typical JFET (3.0 pF), the frequency response for a given input source resistance is greatly enhanced. This becomes evident in D-to-A current to voltage conversion applications where the feedback resistance can form a pole with the input capacitance of the op amp. This input pole creates a 2nd Order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 10 kW of feedback resistance, the MC33171/72/74 family can typically settle to within 1/2 LSB of 8 bits in 4.2 ms, and within 1/2 LSB of 12 bits in 4.8 ms for a 10 V step. In a standard inverting unity gain fast settling configuration, the symmetrical slew rate is typically 2.1 V/ms. In the classic noninverting unity gain configuration the typical output positive slew rate is also 2.1 V/ms, and the corresponding negative slew rate will usually exceed the positive slew rate as a function of the fall time of the input waveform. The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A 10 kW load resistance can typically swing within 0.8 V of the positive rail (VCC) and negative rail (VEE), providing a 28.4 Vpp swing from 15 V supplies. This large output swing becomes most noticeable at lower supply voltages. The positive swing is limited by the saturation voltage of the current source transistor Q7, the VBE of the NPN pull-up transistor Q17, and the voltage drop associated with the short circuit resistance, R5. For sink currents less than 0.4 mA, the negative swing is limited by the saturation voltage of the pull-down transistor Q15, and the voltage drop across R4 and R5. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of VEE. For sink currents (> 0.4 mA), diode D3 clamps the voltage across R4. Thus the negative swing is limited by the saturation voltage of Q15, plus the forward diode drop of D3 (VEE +1.0 V). Therefore an unprecedented peak-to-peak output voltage swing is possible for a given supply voltage as indicated by the output swing specifications. If the load resistance is referenced to VCC instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull-up capability. Because the PNP output emitter-follower transistor has been eliminated, the MC33171/72/74 family offers a 15 mA minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for current switching applications. In addition, the all NPN transistor output stage is inherently faster than PNP types, contributing to the bipolar amplifier's improved gain bandwidth product. The associated high frequency low output impedance (200 W typ @ 1.0 MHz) allows capacitive drive capability from 0 pF to 400 pF without oscillation in the noninverting unity gain configuration. The 60 phase margin and 15 dB gain margin, as well as the general gain and phase characteristics, are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The AC characteristics of the MC33171/72/74 family also allow excellent active filter capability, especially for low voltage single supply applications. Although the single supply specification is defined at 5.0 V, these amplifiers are functional to at least 3.0 V @ 25C. However slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur.
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MC33171, MC33172, MC33174, NCV33172
If power to this integrated circuit is applied in reverse polarity, or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. As usual with most high frequency amplifiers, proper lead dress, component placement and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input/output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous "pick up" at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for 15 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating.
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MC33171, MC33172, MC33174, NCV33172
2.2 k 510 k VCC Cin 100 k + - Vin 1.0 k Vin AV = 101 BW ( -3.0 dB) = 20 kHz AV = 10 BW ( -3.0 dB) = 200 kHz 100 k RL VO 0 CO VO 100 k Cin 100 k 10 k + - 10 k RL 100 k CO VO 3.6 Vpp 100 k VO 0 3.8 Vpp VCC
Figure 10. AC Coupled Noninverting Amplifier with Single +5.0 V Supply
Figure 11. AC Coupled Inverting Amplifier with Single +5.0 V Supply
VCC
100 k 4.7 k 50 k RL
VCC 3 VO 2 + - 4 7 6 5 1 10 k
+ -
100 k
1.0 M
V 2.5 V Vin O AV = 10 BW ( -3.0 dB) = 200 kHz
4.2 Vpp
VEE Offset Nulling range is approximately 80 mV with a 10 k potentiometer, MC33171 only.
Figure 12. DC Coupled Inverting Amplifier Maximum Output Swing with Single +5.0 V Supply
Figure 13. Offset Nulling Circuit
Vin 0.2 Vdc 16 k Vin R 0.01 C 16 k R - + VO Vin R2 5.6 k 2C 0.02 2R 32 k 2C 0.02 fo = 1.0 kHz 1 fo = 4 p RC C 0.047 0.4 VCC R1 1.1 k C 0.047 R3 2.2 k - +
VCC fo = 30 kHz Q = 10 HO = 1.0 VO
Then: R1 =
R3 2 HO
R2 =
R1 R3 4Q2R1 -R3
Qo fo Q Given fo = center frequency R3 = < 0.1 Ao = Gain at center frequency p foC GBW Choose Value fo, Q, Ao, C For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.
Figure 14. Active High-Q Notch Filter
Figure 15. Active Bandpass Filter
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MC33171, MC33172, MC33174, NCV33172
ORDERING INFORMATION
Op Amp Function Operating Device MC33171D MC33171DG MC33171DR2 Single MC33171DR2G MC33171P MC33171PG MC33172D MC33172DG MC33172DR2 MC33172DR2G MC33172P Dual MC33172PG MC33172VD MC33172VDG MC33172VDR2 MC33172VDR2G NCV33172DR2** MC33174D MC33174DG MC33174DR2 MC33174DR2G MC33174DTB MC33174DTBG MC33174DTBR2 Quad MC33174DTBR2G MC33174P MC33174PG MC33174VDR2 MC33174VDR2G MC33174VP MC33174VPG TA = -40 to +125C TA = -40 to +85C TA = -40 to +125C TA = -40 to +85C TA = -40 to +85C Temperature Range Package SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) Plastic DIP Plastic DIP (Pb-Free) SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) Plastic DIP Plastic DIP (Pb-Free) SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) SO-8 SO-14 SO-14 (Pb-Free) SO-14 SO-14 (Pb-Free) TSSOP-14* TSSOP-14* TSSOP-14* TSSOP-14* Plastic DIP Plastic DIP (Pb-Free) SO-14 SO-14 (Pb-Free) Plastic DIP Plastic DIP (Pb-Free) 25 Units/Rail 2500 / Tape & Reel 25 Units/Rail 2500 / Tape & Reel 55 Units/Rail 2500 / Tape & Reel 98 Units/Rail 2500 / Tape & Reel 50 Units/Rail 2500 / Tape & Reel 98 Units/Rail 50 Units/Rail 2500 / Tape & Reel 98 Units/Rail Shipping
96 Units/Rail 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. **NCV prefix for automotive and other applications requiring site and control changes.
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MC33171, MC33172, MC33174, NCV33172
MARKING DIAGRAMS
PDIP-8 P SUFFIX CASE 626 8 MC3317xP AWL YYWWG 1 1 8
SO-8 D SUFFIX CASE 751
SO-8 MC33172VD NCV33172D CASE 751 8
3317x ALYW G 1
3317V ALYW G
PDIP-14 P SUFFIX CASE 646 14 MC33174P AWLYYWWG 1 1 14
PDIP-14 VP SUFFIX CASE 646 14 MC33174VP AWLYYWWG 1
SO-14 D SUFFIX CASE 751A 14 MC33174DG AWLYWW 1
SO-14 VD SUFFIX CASE 751A
MC33174VDG AWLYWW
TSSOP-14 DTB SUFFIX CASE 948G 14 MC33 174 ALYW G G 1
x A WL, L YY, Y WW, W G or G
= 1 or 2 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location)
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MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
PDIP-8 P SUFFIX CASE 626-05 ISSUE L
8
5
-B-
1 4
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10 _ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
F
NOTE 2
-A-
L
C -T-
SEATING PLANE
J N D K
M
M TA B
H
G 0.13 (0.005)
M M
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MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-X-
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.15 (0.006) T U
S
J J1
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
CCC EEE CCC EEE CCC
A -V-
K1
DIM A B C D F G H J J1 K K1 L M
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC33171, MC33172, MC33174, NCV33172
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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16
MC33171/D

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